The present invention relates to an improvement of clock synthesis for multiple channels in Automated Test Equipment (ATE) including phase and frequency synchronization between channels with possibly different frequencies.
Integrated Circuits (IC) generally need to be tested to assure proper operation. This—in particular—is required during IC development and manufacturing. In the latter case, the ICs are usually tested before final application. During test, the IC, as Device Under Test (DUT), is exposed to various types of stimulus signals, and its responses are measured, processed and usually compared to an expected response of a good device. Automated Test Equipments (ATE) usually perform these tasks according to a device-specific test program. Examples for ATE are the Agilent 83000 and 93000 families of Semiconductor Test Systems of Agilent Technologies as disclosed e.g. under http://www.ate.agilent.com/ste/products/intelligent test/SOC test/SOC Tech Oview.shtml. Details of those families are also disclosed e.g. in EP-A-859318, EP-A-864977, EP-A-886214, EP-A-882991, EP-A-1092983, U.S. Pat. Nos. 5,499,248, 5,453,995.
Automated Test Equipment (ATE) is usually structured using cards comprising electronic circuits, each of said cards controlling electrically a couple of pins of said device under test (DUT) with a predetermined signal pattern by test signal processors. A number of cards are arranged in a card cage, respectively, and a number of card cages usually form the ATE.
A frequency reference can be provided centrally from which one or few synchronized master clocks (MCLK) with typically few 100 MHz can be derived and synchronized centrally and distributed to said cards. The card clock (CCLK) can be selected locally at said card from said few master clocks (MCLK).
Alternatively, a clock can be synthesized on card level using a central frequency reference and synchronizing said card clock to a central synchronization signal (SYNC) feeding direct digital synthesis (DDS) and following phase locked loop (PLL).